TY - GEN

T1 - Analysis of cyclic combinational circuits

AU - Malik, Sharad

PY - 1993

Y1 - 1993

N2 - A logic circuit is said to be combinational if the function it computes depends only on the inputs applied to the circuit, and is sequential if it depends on some past history in addition to the current inputs. Circuits that have an underlying topology that is acyclic are combinational, since feedback is a necessary condition for it to be sequential. However, it is not a sufficient condition since there exist combinational logic circuits that are cyclic. These occur often in bus structures in data paths. Traditional formal techniques in logic synthesis, logic analysis and timing analysis of combinational circuits have restricted themselves to acyclic combinational circuits since they have been unable to handle the analysis of circuits with cycles. Thus, in practice, these circuits are handled using clumsy work-arounds, which is obviously undesirable. This paper presents a formal analysis of these circuits, and presents techniques for the logical and timing analysis of such circuits. These techniques are practically feasible on reasonably large circuits encountered in practice.

AB - A logic circuit is said to be combinational if the function it computes depends only on the inputs applied to the circuit, and is sequential if it depends on some past history in addition to the current inputs. Circuits that have an underlying topology that is acyclic are combinational, since feedback is a necessary condition for it to be sequential. However, it is not a sufficient condition since there exist combinational logic circuits that are cyclic. These occur often in bus structures in data paths. Traditional formal techniques in logic synthesis, logic analysis and timing analysis of combinational circuits have restricted themselves to acyclic combinational circuits since they have been unable to handle the analysis of circuits with cycles. Thus, in practice, these circuits are handled using clumsy work-arounds, which is obviously undesirable. This paper presents a formal analysis of these circuits, and presents techniques for the logical and timing analysis of such circuits. These techniques are practically feasible on reasonably large circuits encountered in practice.

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M3 - Conference contribution

AN - SCOPUS:0027832665

SN - 0818644923

T3 - Proc 1993 IEEE ACM Int Conf Comput Aided Des

SP - 618

EP - 625

BT - Proc 1993 IEEE ACM Int Conf Comput Aided Des

A2 - Anon, null

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design

Y2 - 7 November 1993 through 11 November 1993

ER -