A logic circuit is said to be combinational if the function it computes depends only on the inputs applied to the circuit, and is sequential if it depends on some past history in addition to the current inputs. Circuits that have an underlying topology that is acyclic are combinational, since feedback is a necessary condition for them to be sequential. However, it is not a sufficient condition since there exist combinational logic circuits that are cyclic. These occur often in bus structures in data paths. Traditional formal techniques in logic synthesis, logic analysis, and timing analysis of combinational circuits have restricted themselves to acyclic combinational circuits, since they have been unable to handle the analysis of circuits with cycles. Thus, in practice, these circuits are handled using clumsy work-arounds, which is obviously undesirable. This paper presents a formal analysis of these circuits and presents techniques for the logical and timing analysis of such circuits. These techniques are practically feasible on reasonably large circuits encountered in practice.
|Original language||English (US)|
|Number of pages||7|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Jul 1994|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering