TY - JOUR
T1 - An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes
AU - Verma, Naveen
AU - Chandrakasan, Anantha P.
N1 - Funding Information:
Manuscript received June 14, 2006; revised January 30, 2007. This work was supported by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory, under agreement number F33615-02-2-4005. The IC fabrication was provided by National Semiconductor Corporation.
PY - 2007/6
Y1 - 2007/6
N2 - A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 μW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by selftiming the bit-decisions. Prototyped in a 0.18-μxm, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively.
AB - A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 μW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by selftiming the bit-decisions. Prototyped in a 0.18-μxm, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively.
KW - ADC
KW - Analog-to-digital conversion
KW - CMOS analog integrated circuits
KW - Circuit noise
KW - Low-power electronics
KW - Offset compensation
KW - Scaleable
KW - Successive approximation register
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U2 - 10.1109/JSSC.2007.897157
DO - 10.1109/JSSC.2007.897157
M3 - Article
AN - SCOPUS:34249774029
VL - 42
SP - 1196
EP - 1205
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 6
ER -