Abstract
A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 μW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by selftiming the bit-decisions. Prototyped in a 0.18-μxm, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively.
Original language | English (US) |
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Pages (from-to) | 1196-1205 |
Number of pages | 10 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 42 |
Issue number | 6 |
DOIs | |
State | Published - Jun 1 2007 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Keywords
- ADC
- Analog-to-digital conversion
- CMOS analog integrated circuits
- Circuit noise
- Low-power electronics
- Offset compensation
- Scaleable
- Successive approximation register