An operation placement and scheduling scheme for cache and communication localities in fine-grain parallel architectures

Computer Science

• Memory Access 100%
• Scheduling Scheme 100%
• Parallel Architectures 100%
• Parallelism 50%
• Memory System 50%
• Program Execution 50%
• Concurrency 50%
• Computational Power 50%
• Motion Estimation 50%
• block matching algorithm 50%
• Parallel System 50%
• Communication Bandwidth 50%
• Intensive Computation 50%
• External Memory 50%
• Data Partition 50%
• Data Partitioning 50%
• Microprocessor Chips 50%
• Compiler 50%

Keyphrases

• Computer Platform 50%