An operation placement and scheduling scheme for cache and communication localities in fine-grain parallel architectures

Yen Kuang Chen, S. Y. Kung

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

With increasing on-chip hardware, concurrency is a way to bridge the gap between the computational power demanded by the applications and that afforded by the computer platforms. Although parallel systems are increasingly popular they remain very difficult to program. In fact, most compilers require the programmer to specify how to partition data or map program code to the system's processors. To ensure an effective program, cache locality is important because of the large speed gap between microprocessors and memory systems. It is also important to make use of local communication whenever possible, since it is cheaper faster and less power hungry than global communication. In order to exploit these locality properties, we present a systematic operation placement and scheduling scheme for fine-grain parallel architectures. The key advantages are twofolds: (1) This multiprojection method, which deals with multidimensional parallelism systematically, can alleviate the burden of the programmer in coding and data partitioning. (2) it addresses the memory/communication bandwidth bottleneck, and can lend to faster program execution. On a special design example of the motion estimation block-matching algorithm, which requires the most intensive computation and memory accesses in video coding, our method lends to a reduction of external memory accesses by two to three orders of magnitude.

Original languageEnglish (US)
Pages390-396
Number of pages7
DOIs
StatePublished - Jan 1 1997
Event3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997 - Taipei, Taiwan, Province of China
Duration: Dec 18 1997Dec 20 1997

Other

Other3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997
CountryTaiwan, Province of China
CityTaipei
Period12/18/9712/20/97

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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    Chen, Y. K., & Kung, S. Y. (1997). An operation placement and scheduling scheme for cache and communication localities in fine-grain parallel architectures. 390-396. Paper presented at 3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997, Taipei, Taiwan, Province of China. https://doi.org/10.1109/ISPAN.1997.645125