TY - GEN
T1 - An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS
AU - Lu, Xuyang
AU - Hong, Lingyu
AU - Sengupta, Kaushik
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/3/2
Y1 - 2017/3/2
N2 - Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically uncontrollable process variations and therefore, can uniquely authenticate each die to counteract counterfeit, piracy or sabotage. Classically, PUF architectures have exploited process variations affecting transistor-level active device performances such as process-dependent gate delays and interconnect delays, SRAM and inverter maximum gain points, and ring oscillator frequencies [1]-[6]. While active device variations have been exploited to generate PUF signatures, they are susceptible to noise, external perturbations and aging. Since the resultant process variant responses are typically normally distributed, to spread the variance of the distribution and decrease the number of challenges near the unstable decision region, we propose a method to exploit passive variations within the chip in addition to active device variations. While lithographic variations in the smallest metal features may not influence the electrical performance drastically, their effects can be amplified at optical frequencies with wavelengths comparable to the minimal feature size. In fact, before the concept of electronic PUFs were demonstrated in silicon, one of the first implementations of strong PUFs was demonstrated in the optical domain, which exploited speckle-patterns of a random scattering medium in the presence of a laser light. In this work, we present the first CMOS-based opto-active PUF, which not only utilizes the active variations, but also amplifies the lithographic variation of passive metal structures through process-sensitive copper-based CMOS integrated photonic crystals. The measured CMOS chip achieves a native Inter-PUF/Intra-PUF Hamming Distance (HD) ratio of 198X without any post-operation.
AB - Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically uncontrollable process variations and therefore, can uniquely authenticate each die to counteract counterfeit, piracy or sabotage. Classically, PUF architectures have exploited process variations affecting transistor-level active device performances such as process-dependent gate delays and interconnect delays, SRAM and inverter maximum gain points, and ring oscillator frequencies [1]-[6]. While active device variations have been exploited to generate PUF signatures, they are susceptible to noise, external perturbations and aging. Since the resultant process variant responses are typically normally distributed, to spread the variance of the distribution and decrease the number of challenges near the unstable decision region, we propose a method to exploit passive variations within the chip in addition to active device variations. While lithographic variations in the smallest metal features may not influence the electrical performance drastically, their effects can be amplified at optical frequencies with wavelengths comparable to the minimal feature size. In fact, before the concept of electronic PUFs were demonstrated in silicon, one of the first implementations of strong PUFs was demonstrated in the optical domain, which exploited speckle-patterns of a random scattering medium in the presence of a laser light. In this work, we present the first CMOS-based opto-active PUF, which not only utilizes the active variations, but also amplifies the lithographic variation of passive metal structures through process-sensitive copper-based CMOS integrated photonic crystals. The measured CMOS chip achieves a native Inter-PUF/Intra-PUF Hamming Distance (HD) ratio of 198X without any post-operation.
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U2 - 10.1109/ISSCC.2017.7870366
DO - 10.1109/ISSCC.2017.7870366
M3 - Conference contribution
AN - SCOPUS:85016272774
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 272
EP - 273
BT - 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
A2 - Fujino, Laura C.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Y2 - 5 February 2017 through 9 February 2017
ER -