An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS

Xuyang Lu, Lingyu Hong, Kaushik Sengupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically uncontrollable process variations and therefore, can uniquely authenticate each die to counteract counterfeit, piracy or sabotage. Classically, PUF architectures have exploited process variations affecting transistor-level active device performances such as process-dependent gate delays and interconnect delays, SRAM and inverter maximum gain points, and ring oscillator frequencies [1]-[6]. While active device variations have been exploited to generate PUF signatures, they are susceptible to noise, external perturbations and aging. Since the resultant process variant responses are typically normally distributed, to spread the variance of the distribution and decrease the number of challenges near the unstable decision region, we propose a method to exploit passive variations within the chip in addition to active device variations. While lithographic variations in the smallest metal features may not influence the electrical performance drastically, their effects can be amplified at optical frequencies with wavelengths comparable to the minimal feature size. In fact, before the concept of electronic PUFs were demonstrated in silicon, one of the first implementations of strong PUFs was demonstrated in the optical domain, which exploited speckle-patterns of a random scattering medium in the presence of a laser light. In this work, we present the first CMOS-based opto-active PUF, which not only utilizes the active variations, but also amplifies the lithographic variation of passive metal structures through process-sensitive copper-based CMOS integrated photonic crystals. The measured CMOS chip achieves a native Inter-PUF/Intra-PUF Hamming Distance (HD) ratio of 198X without any post-operation.

Original languageEnglish (US)
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages272-273
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - Mar 2 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: Feb 5 2017Feb 9 2017

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Country/TerritoryUnited States
CitySan Francisco
Period2/5/172/9/17

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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