An efficient, practical parallelization methodology for multicore architecture simulation

James Donald, Margaret Martonosi

Research output: Contribution to journalArticlepeer-review

30 Scopus citations


Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and research, multiple core processor simulation environments are necessary. A well-known positive feedback property of computer design is that we use today's computers to design tomorrow's. Thus, with the emergence of chip multi-processors, it is natural to re-examine simulation environments written to exploit parallelism. In this paper we present a programming methodology for directly converting existing uniprocessor simulators into parallelized multiple-core simulators. Our method not only takes significantly less development effort compared to some prior used programming techniques, but also possesses advantages by retaining a modular and comprehensible programming structure. We demonstrate our case with actual developed products after applying this method to two different simulators, one developed from IBM Turandot and the other from the SimpleScalar tool set. Our SimpleScalar-based framework achieves a parallel speedup of 2.2X on a dual-CPU dual-core (4-way) Opteron server.

Original languageEnglish (US)
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - Feb 2006

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


Dive into the research topics of 'An efficient, practical parallelization methodology for multicore architecture simulation'. Together they form a unique fingerprint.

Cite this