An edge-endpoint-based configurable hardware architecture for VLSI CAD layout design rule checking

Zhen Luo, Margaret Rose Martonosi, Pranav Ashar

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

Design rule checking (DRC) is an important step in VLSI design in which the widths and spacings of design features in a VLSI circuit layout are checked against the design rules of a particular fabrication process. In the past, some efforts to build hardware accelerators for DRC have been proposed, but these efforts were hobbled by the fact that it is often impractical to build a different rule-checking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. Because the rule-checking is built in configurable hardware, it can garner impressive speedups over software approaches, while retaining the flexibility needed to easily change the rule checker as rules or processes change. Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking; this approach is particularly well-suited to the constraints of configurable hardware. Although design rules do change over time, their intrinsic similarity allows us to propose a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for the MOSIS SCN4N_SUB process. The hardware required per rule is quite small; we have implemented several design rule checks within a single Xilinx XC4013 FPGA. Our hardware, implemented on a Pamette board, runs at a clock rate of 33MHz. We also compare the performance of our approach to software methods and demonstrate overall speedups in excess of 25X.

Original languageEnglish (US)
Pages (from-to)158-167
Number of pages10
JournalIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
StatePublished - Dec 1 1999
EventProceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCMM 1999) - Napa Valley, CA, United States
Duration: Apr 21 1999Apr 23 1999

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)

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