An automatic test pattern generation framework for combinational threshold logic networks

Pallav Gupta, Rui Zhang, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs) and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors, ICCD 2004
Pages540-543
Number of pages4
DOIs
StatePublished - 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

OtherProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
CountryUnited States
CitySan Jose, CA
Period10/11/0410/13/04

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'An automatic test pattern generation framework for combinational threshold logic networks'. Together they form a unique fingerprint.

  • Cite this

    Gupta, P., Zhang, R., & Jha, N. K. (2004). An automatic test pattern generation framework for combinational threshold logic networks. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 (pp. 540-543). (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2004.1347974