An architecture framework for introducing predicated execution into embedded microprocessors

Daniel A. Connors; Jean Michel Puiatti; David I. August; Kevin M. Crozier; Wen Mei W. Hwu

doi:10.1007/3-540-48311-x_185

An architecture framework for introducing predicated execution into embedded microprocessors

Daniel A. Connors, Jean Michel Puiatti, David I. August, Kevin M. Crozier, Wen Mei W. Hwu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism (ILP) techniques that are traditionally used in high performance systems. Predicated execution, an important ILP technique, can be used to improve branch handling, reduce frequently mispredicted branches, and expose multiple execution paths to hardware resources. However, there is a major tradeoff in the design of the instruction set, the addition of a predicate operand for all instructions. We propose a new architecture framework for introducing predicated execution to embedded designs. Experimental results show a 10% performance improvement and a code reduction of 25% over a traditionally predicated architecture.

Original language	English (US)
Title of host publication	Euro-Par 1999 - Parallel Processing
Subtitle of host publication	5th International Conference, Proceedings
Publisher	Springer Verlag
Pages	1301-1311
Number of pages	11
ISBN (Print)	3540664432, 9783540664437
DOIs	https://doi.org/10.1007/3-540-48311-x_185
State	Published - 1999
Externally published	Yes
Event	5th International Conference on Parallel Processing, Euro-Par 1999 - Toulouse, France Duration: Aug 31 1999 → Sep 3 1999

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	1685 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	5th International Conference on Parallel Processing, Euro-Par 1999
Country/Territory	France
City	Toulouse
Period	8/31/99 → 9/3/99

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/3-540-48311-x_185

Cite this

Connors, D. A., Puiatti, J. M., August, D. I., Crozier, K. M., & Hwu, W. M. W. (1999). An architecture framework for introducing predicated execution into embedded microprocessors. In Euro-Par 1999 - Parallel Processing: 5th International Conference, Proceedings (pp. 1301-1311). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1685 LNCS). Springer Verlag. https://doi.org/10.1007/3-540-48311-x_185

Connors, Daniel A. ; Puiatti, Jean Michel ; August, David I. et al. / An architecture framework for introducing predicated execution into embedded microprocessors. Euro-Par 1999 - Parallel Processing: 5th International Conference, Proceedings. Springer Verlag, 1999. pp. 1301-1311 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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author = "Connors, {Daniel A.} and Puiatti, {Jean Michel} and August, {David I.} and Crozier, {Kevin M.} and Hwu, {Wen Mei W.}",

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Connors, DA, Puiatti, JM, August, DI, Crozier, KM & Hwu, WMW 1999, An architecture framework for introducing predicated execution into embedded microprocessors. in Euro-Par 1999 - Parallel Processing: 5th International Conference, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 1685 LNCS, Springer Verlag, pp. 1301-1311, 5th International Conference on Parallel Processing, Euro-Par 1999, Toulouse, France, 8/31/99. https://doi.org/10.1007/3-540-48311-x_185

An architecture framework for introducing predicated execution into embedded microprocessors. / Connors, Daniel A.; Puiatti, Jean Michel; August, David I. et al.
Euro-Par 1999 - Parallel Processing: 5th International Conference, Proceedings. Springer Verlag, 1999. p. 1301-1311 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1685 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism (ILP) techniques that are traditionally used in high performance systems. Predicated execution, an important ILP technique, can be used to improve branch handling, reduce frequently mispredicted branches, and expose multiple execution paths to hardware resources. However, there is a major tradeoff in the design of the instruction set, the addition of a predicate operand for all instructions. We propose a new architecture framework for introducing predicated execution to embedded designs. Experimental results show a 10% performance improvement and a code reduction of 25% over a traditionally predicated architecture.

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Connors DA, Puiatti JM, August DI, Crozier KM, Hwu WMW. An architecture framework for introducing predicated execution into embedded microprocessors. In Euro-Par 1999 - Parallel Processing: 5th International Conference, Proceedings. Springer Verlag. 1999. p. 1301-1311. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-48311-x_185

An architecture framework for introducing predicated execution into embedded microprocessors

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