TY - GEN
T1 - An analysis of efficient multi-core global power management policies
T2 - 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
AU - Isci, Canturk
AU - Buyuktosunoglu, Alper
AU - Cher, Chen Yong
AU - Bose, Pradip
AU - Martonosi, Margaret Rose
PY - 2006
Y1 - 2006
N2 - Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core control of power levels (modes) is possible, a global power manager should be able to dynamically set the modes suitably. This would be done in tune with the workload characteristics, in order to always maintain a chip-level power that is below the specified budget. Furthermore, this should be possible without significant degradation of chip-level throughput performance. We analyze and validate this concept in detail in this paper. We assume a per-core DVFS (dynamic voltage and frequency scaling) knob to be available to such a conceptual global power manager. We evaluate several different policies for global multi-core power management. In this analysis, we consider various different objectives such as prioritization and optimized throughput. Overall, our results show that in the context of a workload comprised of SPEC benchmark threads, our best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget. Furthermore, we show that these global dynamic management policies perform significantly better than static management, even if static scheduling is given oracular knowledge.
AB - Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core control of power levels (modes) is possible, a global power manager should be able to dynamically set the modes suitably. This would be done in tune with the workload characteristics, in order to always maintain a chip-level power that is below the specified budget. Furthermore, this should be possible without significant degradation of chip-level throughput performance. We analyze and validate this concept in detail in this paper. We assume a per-core DVFS (dynamic voltage and frequency scaling) knob to be available to such a conceptual global power manager. We evaluate several different policies for global multi-core power management. In this analysis, we consider various different objectives such as prioritization and optimized throughput. Overall, our results show that in the context of a workload comprised of SPEC benchmark threads, our best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget. Furthermore, we show that these global dynamic management policies perform significantly better than static management, even if static scheduling is given oracular knowledge.
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U2 - 10.1109/MICRO.2006.8
DO - 10.1109/MICRO.2006.8
M3 - Conference contribution
AN - SCOPUS:36949001469
SN - 0769527329
SN - 9780769527321
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
SP - 347
EP - 358
BT - Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
Y2 - 9 December 2006 through 13 December 2006
ER -