An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget

Canturk Isci, Alper Buyuktosunoglu, Chen Yong Cher, Pradip Bose, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

427 Scopus citations

Abstract

Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core control of power levels (modes) is possible, a global power manager should be able to dynamically set the modes suitably. This would be done in tune with the workload characteristics, in order to always maintain a chip-level power that is below the specified budget. Furthermore, this should be possible without significant degradation of chip-level throughput performance. We analyze and validate this concept in detail in this paper. We assume a per-core DVFS (dynamic voltage and frequency scaling) knob to be available to such a conceptual global power manager. We evaluate several different policies for global multi-core power management. In this analysis, we consider various different objectives such as prioritization and optimized throughput. Overall, our results show that in the context of a workload comprised of SPEC benchmark threads, our best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget. Furthermore, we show that these global dynamic management policies perform significantly better than static management, even if static scheduling is given oracular knowledge.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
Pages347-358
Number of pages12
DOIs
StatePublished - Dec 1 2006
Event39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 - Orlando, FL, United States
Duration: Dec 9 2006Dec 13 2006

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
CountryUnited States
CityOrlando, FL
Period12/9/0612/13/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Isci, C., Buyuktosunoglu, A., Cher, C. Y., Bose, P., & Martonosi, M. R. (2006). An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 (pp. 347-358). [4041859] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2006.8