An algorithm for nanopipelining of RTD-based circuits and architectures

Pallav Gupta, Niraj Kumar Jha

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

In this study, an algorithm to postprocess a register-transfer-level architecture to enable gate-level pipelining or nanopipelining is presented. Nanopipelining is well suited for the nanotechnology based on resonant-tunneling diodes (RTDs) and offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing. Since RTDs are a self-latching nanoscale device, nanopipelining is an implicit property that should be exploited for this technology. This study explores and addresses the benefits of nanopipelining and presents an algorithm for architectural nanopipelining.

Original languageEnglish (US)
Pages (from-to)159-167
Number of pages9
JournalIEEE Transactions on Nanotechnology
Volume4
Issue number2
DOIs
StatePublished - Mar 1 2005

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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