@inproceedings{fdcf492288c946e69a37aa361f48ed3b,
title = "An algorithm for nano-pipelining of circuits and architectures for a nanotechnology",
abstract = "In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.",
author = "Pallav Gupta and Jha, \{Niraj K.\}",
year = "2004",
doi = "10.1109/DATE.2004.1269019",
language = "English (US)",
isbn = "0769520855",
series = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition",
pages = "974--979",
editor = "G. Gielen and J. Figueras",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04",
note = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 ; Conference date: 16-02-2004 Through 20-02-2004",
}