An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

Pallav Gupta; Niraj K. Jha

doi:10.1109/DATE.2004.1269019

An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

Pallav Gupta, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.

Original language	English (US)
Title of host publication	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Editors	G. Gielen, J. Figueras
Pages	974-979
Number of pages	6
DOIs	https://doi.org/10.1109/DATE.2004.1269019
State	Published - 2004
Event	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France Duration: Feb 16 2004 → Feb 20 2004

Publication series

Name	Proceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume	2

Other

Other	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Country/Territory	France
City	Paris
Period	2/16/04 → 2/20/04

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/DATE.2004.1269019

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Gupta, P., & Jha, N. K. (2004). An algorithm for nano-pipelining of circuits and architectures for a nanotechnology. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 974-979). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 2). https://doi.org/10.1109/DATE.2004.1269019

@inproceedings{fdcf492288c946e69a37aa361f48ed3b,

title = "An algorithm for nano-pipelining of circuits and architectures for a nanotechnology",

abstract = "In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.",

author = "Pallav Gupta and Jha, {Niraj K.}",

year = "2004",

doi = "10.1109/DATE.2004.1269019",

language = "English (US)",

isbn = "0769520855",

series = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition",

pages = "974--979",

editor = "G. Gielen and J. Figueras",

booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04",

note = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 ; Conference date: 16-02-2004 Through 20-02-2004",

}

Gupta, P & Jha, NK 2004, An algorithm for nano-pipelining of circuits and architectures for a nanotechnology. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 974-979, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 2/16/04. https://doi.org/10.1109/DATE.2004.1269019

An algorithm for nano-pipelining of circuits and architectures for a nanotechnology. / Gupta, Pallav; Jha, Niraj K.
Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. 2004. p. 974-979 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

AU - Gupta, Pallav

AU - Jha, Niraj K.

PY - 2004

Y1 - 2004

N2 - In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.

AB - In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.

UR - http://www.scopus.com/inward/record.url?scp=3042558150&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=3042558150&partnerID=8YFLogxK

U2 - 10.1109/DATE.2004.1269019

DO - 10.1109/DATE.2004.1269019

M3 - Conference contribution

AN - SCOPUS:3042558150

SN - 0769520855

SN - 9780769520858

T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition

SP - 974

EP - 979

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

A2 - Gielen, G.

A2 - Figueras, J.

T2 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

Y2 - 16 February 2004 through 20 February 2004

ER -

An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

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