An algorithm for nano-pipelining of circuits and architectures for a nanotechnology

Pallav Gupta, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Pages974-979
Number of pages6
DOIs
StatePublished - Jul 12 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Publication series

NameProceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume2

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Gupta, P., & Jha, N. K. (2004). An algorithm for nano-pipelining of circuits and architectures for a nanotechnology. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 974-979). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 2). https://doi.org/10.1109/DATE.2004.1269019