Amorphous silicon floating-gate thin film transistor

Yifei Huang, Bahman Hekmatshoar, Sigurd Wagner, James Christopher Sturm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Amorphous silicon (a-Si) based memory devices have the potential to greatly expand the functionality of a-Si thin-film transistor (TFT) circuitry. Recently, an a-Si floating gate TFT (FGTFT) based memory element has been demonstrated, but the memory window was only 0.5V an d the retention time was only ∼1hour [1]. Furthermore, a-Si FGTFTs in general have a threshold voltage which depends on the drain voltage. In this work, we explore the effects of tunnel dielectric deposition condition and floating gate (FG) geometry on the performance of a-Si FGTFT. Through this analysis, we achieved a-Si FGTFTs with memory windows of >4V, room temperature retention times of >150hours and threshold voltages (VT) which are independent of the drain voltage.

Original languageEnglish (US)
Title of host publication67th Device Research Conference, DRC 2009
Pages135-136
Number of pages2
DOIs
StatePublished - Dec 11 2009
Event67th Device Research Conference, DRC 2009 - University Park, PA, United States
Duration: Jun 22 2009Jun 24 2009

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

Other67th Device Research Conference, DRC 2009
CountryUnited States
CityUniversity Park, PA
Period6/22/096/24/09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Huang, Y., Hekmatshoar, B., Wagner, S., & Sturm, J. C. (2009). Amorphous silicon floating-gate thin film transistor. In 67th Device Research Conference, DRC 2009 (pp. 135-136). [5354877] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2009.5354877