ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology

Wei Zhang; Niraj K. Jha

doi:10.1109/ICCD.2005.21

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology

Wei Zhang, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

Since rapid progress has been made in device improvement and integration of small carbon nanotube field-effect transistors (CNFETs) circuits, the time has come for developing computer-aided design (CAD) methodologies and tools for the design of larger CNFET circuits. In this paper, we present the first automatic logic-to-layout (ALLCN) tool for CNFET circuits. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and design tools for such devices. ALLCN is built on top of existing CAD tools including Magic, TimberWolf and YACR. It can automatically generate a CNFET circuit layout from a logic implementation and then perform circuit extraction from the physical layout for SPICE simulation. Experiments were performed with various MCNC benchmarks and logic blocks. Their performance, area and power are reported.

Original language	English (US)
Title of host publication	Proceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2005
Pages	281-288
Number of pages	8
DOIs	https://doi.org/10.1109/ICCD.2005.21
State	Published - 2005
Event	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States Duration: Oct 2 2005 → Oct 5 2005

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2005
ISSN (Print)	1063-6404

Other

Other	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/Territory	United States
City	San Jose, CA
Period	10/2/05 → 10/5/05

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2005.21

Cite this

Zhang, W., & Jha, N. K. (2005). ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 281-288). Article 1524166 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.21

@inproceedings{02cc91ef781940e490e7976827e50145,

title = "ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology",

abstract = "Since rapid progress has been made in device improvement and integration of small carbon nanotube field-effect transistors (CNFETs) circuits, the time has come for developing computer-aided design (CAD) methodologies and tools for the design of larger CNFET circuits. In this paper, we present the first automatic logic-to-layout (ALLCN) tool for CNFET circuits. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and design tools for such devices. ALLCN is built on top of existing CAD tools including Magic, TimberWolf and YACR. It can automatically generate a CNFET circuit layout from a logic implementation and then perform circuit extraction from the physical layout for SPICE simulation. Experiments were performed with various MCNC benchmarks and logic blocks. Their performance, area and power are reported.",

author = "Wei Zhang and Jha, {Niraj K.}",

year = "2005",

doi = "10.1109/ICCD.2005.21",

language = "English (US)",

isbn = "0769524516",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

pages = "281--288",

booktitle = "Proceedings - 2005 IEEE International Conference on Computer Design",

note = "2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 ; Conference date: 02-10-2005 Through 05-10-2005",

}

Zhang, W & Jha, NK 2005, ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. in Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524166, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 281-288, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 10/2/05. https://doi.org/10.1109/ICCD.2005.21

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. / Zhang, Wei; Jha, Niraj K.
Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 281-288 1524166 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Zhang, Wei

AU - Jha, Niraj K.

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AB - Since rapid progress has been made in device improvement and integration of small carbon nanotube field-effect transistors (CNFETs) circuits, the time has come for developing computer-aided design (CAD) methodologies and tools for the design of larger CNFET circuits. In this paper, we present the first automatic logic-to-layout (ALLCN) tool for CNFET circuits. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and design tools for such devices. ALLCN is built on top of existing CAD tools including Magic, TimberWolf and YACR. It can automatically generate a CNFET circuit layout from a logic implementation and then perform circuit extraction from the physical layout for SPICE simulation. Experiments were performed with various MCNC benchmarks and logic blocks. Their performance, area and power are reported.

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ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology

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