Since rapid progress has been made in device improvement and integration of small carbon nanotube field-effect transistors (CNFETs) circuits, the time has come for developing computer-aided design (CAD) methodologies and tools for the design of larger CNFET circuits. In this paper, we present the first automatic logic-to-layout (ALLCN) tool for CNFET circuits. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and design tools for such devices. ALLCN is built on top of existing CAD tools including Magic, TimberWolf and YACR. It can automatically generate a CNFET circuit layout from a logic implementation and then perform circuit extraction from the physical layout for SPICE simulation. Experiments were performed with various MCNC benchmarks and logic blocks. Their performance, area and power are reported.