A time-proven method for analyzing the response of a circuit under test is to use a response compression technique, such as a linear feedback shift register (LFSR) used as a signature analyser. Most of the previous work on analysis of signature analysers assume a feedback register structure, and are based on complex coding and simulation results. In this paper, a much simpler model for computing the aliasing probability for any linear finite state machine (LFSM) used as a multiple-input signature analyzer (MISA) is presented. It is shown that the whole class of cyclic LFSM's has identical transient as well as steady-state aliasing probability under the uniform error model as that of any LFSR when used as an MISA. Some other functional circuits, such as accumulators, can also be used for data compression with similar performance as that of any LFSR. Finally, the steady-state aliasing probability is derived for an LFSM used as an MISA under arbitrary error models.