AI-Enabled Design Space Discovery and End-to-End Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mm-Wave/sub-THz PAs between 30 and 120GHz

Jonathan Zhou, Emir Ali Karahan, Sherif Ghozzy, Zheng Liu, Hossein Jalili, Kaushik Sengupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an AI-enabled algorithmic flow for architecture discovery, circuit topology and parameter optimization for RFICs, particularly exploring design spaces beyond human intuition. RF and mmWave IC design is a complex iterative design process that involves co-design of circuits and electromagnetics (EM), including matching networks (MN), combiners, splitters, hybrids, baluns, switches, diplexers, beamforming networks, antennas, and the like. Design of such high-frequency circuits and EM structures has historically relied on intuitive and analytical approaches with starting template architectures. However, there is no reason to believe that such pre-selected topologies are close to achieving the optimal performance in the space of all possible circuit and EM topologies. Consider the design of a typical RFIC, such as a mmWave PA illustrated in Fig. 25.3.1. The design decision typically starts from output power requirements that determine the transistor sizes given the supply voltage. For efficient generation of high output power that requires a very high impedance transformation ratio, power combining may be necessary. Optimizing power combining and MN design is done through a series of trial-and-error processes taking losses, size and bandwidth into account. This iterative process is repeated for driver cells, inter-stage matching, and input splitters, and again with extracted layouts and EM simulations. This approach not only limits the design space to a small set of pre-fixed templates, but the design time can also be significant. Here, we propose an approach for an algorithmic design flow for RF/mmWave ICs, that allows: 1) architecture selection, circuit topology and parameter optimization, and inverse EM synthesis in a nonintuitive design space, and 2) drastic reduction of total design time by eliminating unnecessary iterative design processes. We demonstrate this methodology for a broadband mmWave and sub-THz PA, spanning 34-to-70GHz with peak Psat of 21.2dBm, PAEmax of 26%, and a 100-to-120GHz sub-THz PA with peak Psat of 12.6dBm. Compared to prior works on optimizing circuit parameters with simulation based analog low-frequency circuits [1,2] or passive synthesis with human-designed architecture and circuits [3], this is the first work that demonstrates an end-to-end RFIC AI-enabled synthesis with both active and passive optimization, and from specifications to layout with fabricated and measured results.

Original languageEnglish (US)
Title of host publication2025 IEEE International Solid-State Circuits Conference, ISSCC 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331541019
DOIs
StatePublished - 2025
Event72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francisco, United States
Duration: Feb 16 2025Feb 20 2025

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference72nd IEEE International Solid-State Circuits Conference, ISSCC 2025
Country/TerritoryUnited States
CitySan Francisco
Period2/16/252/20/25

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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