Accurate leakage estimation for FinFET standard cells using the response surface methodology

Keyphrases

• Analytical Model 100%
• Fin Field-effect Transistor (FinFET) 100%
• Response Surface Methodology 100%
• Leakage Assessment 100%
• Logic Gates 66%
• Technology Node 66%
• Multigate Transistor 66%
• 3D Devices 66%
• TCAD Simulation 66%
• Optimization Methods 33%
• Design Basis 33%
• Order of Magnitude 33%
• Device Behavior 33%
• Design Techniques 33%
• CPU Time 33%
• Device Performance 33%
• Circuit Design 33%
• Fabrication Methods 33%
• Modeling Techniques 33%
• Leakage Current 33%
• Power Cost 33%
• Fin Width 33%
• Error Range 33%
• Leakage Power 33%
• Independent Gate FinFET 33%
• Leakage Model 33%
• Central Composite Rotatable Design 33%
• 2D Devices 33%
• Root Mean Square Error 33%
• Logic Styles 33%
• Environmental Variability 33%
• Circuit Optimization 33%
• Leakage Characterization 33%
• Low Leakage Power 33%
• Gate Oxide Thickness 33%
• Gate Length 33%
• Timing Characterization 33%
• Cost-effective Fabrication 33%
• Tri-gate 33%
• 2D to 3D 33%
• FinFET Devices 33%
• Gate Work Function 33%
• Short Gate 33%
• Quasi-Monte Carlo Simulation 33%

Engineering

• Analytical Model 100%
• Response Surface Methodology 100%
• Nodes 66%
• Logic Gate 66%
• Transistor 66%
• Simulation Result 33%
• Cross Section 33%
• Device Behavior 33%
• Device Performance 33%
• Circuit Design 33%
• Optimization Technique 33%
• Electric Power Utilization 33%
• Design Technique 33%
• Oxide Thickness 33%
• Fin Thickness 33%
• Root Mean Square Error 33%
• Field Effect Transistor 33%
• Circuit Designer 33%
• Gate Length 33%
• Gate Oxide 33%

Material Science

• Transistor 100%
• Electronic Circuit 100%
• Field Effect Transistor 50%
• Oxide Thickness 50%