Accurate leakage estimation for FinFET standard cells using the response surface methodology

Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Among different multi-gate transistors, FinFETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current in FinFET standard cells under the effect of variations in gate length (L G), fin thickness (T SI), gate-oxide thickness (T OX) and gate-workfunction (Φ G). To the best of our knowledge, this is the first attempt to develop analytical models for leakage estimation of FinFET devices/logic gates based on TCAD simulations of adjusted 2D device cross-sections that have been shown to track TCAD simulations of 3D device behavior within a 1-3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage models for different logic styles, e.g., shorted-gate (SG) and independent-gate (IG) FinFETs, at the 22nm technology node. The leakage estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results obtained for different adjusted-2D (3D) devices/logic gates with a maximum root mean square error (RMSE) of 5.28% (7.03%).

Original languageEnglish (US)
Title of host publicationProceedings - 25th International Conference on VLSI Design, VLSI Design 2012 - Held Jointly with 11th International Conference on Embedded Systems
Pages238-244
Number of pages7
DOIs
StatePublished - Apr 24 2012
Event25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems - Hyderabad, India
Duration: Jan 7 2012Jan 11 2012

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems
CountryIndia
CityHyderabad
Period1/7/121/11/12

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chaudhuri, S., Mishra, P., & Jha, N. K. (2012). Accurate leakage estimation for FinFET standard cells using the response surface methodology. In Proceedings - 25th International Conference on VLSI Design, VLSI Design 2012 - Held Jointly with 11th International Conference on Embedded Systems (pp. 238-244). [6167758] (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2012.77