A Universal Test Set for CMOS Circuits

This paper addresses the problem of finding a universal test set for CMOS circuits, which can be derived from the functional description alone. It is shown that for a restricted class of CMOS circuits, the gate-level universal test set (UTSg) consisting of maximal false vectors and minimal true vectors can sensitize every detectable stuck-open fault in the circuit. A universal initialization set (UIS) is defined which can also be derived from just the functional description, and which contains initialization vectors for each of the test vectors. This set consists of maximal true vectors and minimal false vectors. It is shown that a test set based on UTSg and UIS can be guaranteed to detect every detectable stuck-open fault in both redundant and irredundant CMOS implementations of the function, even in the presence of arbitrary delays and timing-skews. The size of the test set is also investigated.