A unified systolic architecture for artificial neural networks

This paper proposes a generic iterative model for a wide variety of artificial neural networks (ANNs), single-layer feedback networks, multilayer feed-forward networks, and hierarchical competitive networks, as well as some probabilistic models. A unified formulation is provided for both the retrieving and the learning phases of most ANNs. On the basis of the formulation, a programmable ring systolic array is developed. The architecture maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. It may be adopted as a basic structure for a universal neurocomputer architecture.