TY - GEN

T1 - A totally self-checking checker for a parallel unordered coding scheme

AU - Burns, S. W.

AU - Jha, N. K.

N1 - Funding Information:
*Acknowledgment: This work WM supportedby National Sci- ence Foundation under Grant No. MIP-9010433.
Funding Information:
This work was supported by National Science Foundation under Grant No. MIP-9010433.
Publisher Copyright:
© 1992 IEEE.

PY - 1992

Y1 - 1992

N2 - Bose has developed a parallel unordered coding scheme using only r checkbits for 2r information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all-0's and all-1's need to be transformed to two other information symbols. This allows one to reduce the number of checkbits over Berger code by 1. Since information symbols containing a power-of-two number of bits are quite common, this coding scheme should become quite popular. In this paper, a modular, economical and easily testable totally self-checking (TSC) checker design for the above code is described. The TSC concept is well-known for providing concurrent error detection of transient as well as permanent faults. The design is self-testing with at most only 2r+16 codeword tests. This means that if k is the number of information bits, the size of the codeword test is only O(log2k). This is the first known TSC checker design for this code.

AB - Bose has developed a parallel unordered coding scheme using only r checkbits for 2r information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all-0's and all-1's need to be transformed to two other information symbols. This allows one to reduce the number of checkbits over Berger code by 1. Since information symbols containing a power-of-two number of bits are quite common, this coding scheme should become quite popular. In this paper, a modular, economical and easily testable totally self-checking (TSC) checker design for the above code is described. The TSC concept is well-known for providing concurrent error detection of transient as well as permanent faults. The design is self-testing with at most only 2r+16 codeword tests. This means that if k is the number of information bits, the size of the codeword test is only O(log2k). This is the first known TSC checker design for this code.

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U2 - 10.1109/VTEST.1992.232743

DO - 10.1109/VTEST.1992.232743

M3 - Conference contribution

AN - SCOPUS:85066890941

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 165

EP - 170

BT - Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992

PB - IEEE Computer Society

T2 - 1992 IEEE VLSI Test Symposium, VLSI 1992

Y2 - 7 April 1992 through 9 April 1992

ER -