TY - GEN
T1 - A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding
AU - Tian, Yue
AU - Fok, Mable P.
AU - Prucnal, Paul Richard
PY - 2013/11/18
Y1 - 2013/11/18
N2 - We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.
AB - We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.
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M3 - Conference contribution
AN - SCOPUS:84887497042
SN - 9781557529725
T3 - CLEO: Science and Innovations, CLEO_SI 2013
BT - CLEO
T2 - CLEO: Science and Innovations, CLEO_SI 2013
Y2 - 9 June 2013 through 14 June 2013
ER -