A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

Yue Tian, Mable P. Fok, Paul Richard Prucnal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.

Original languageEnglish (US)
Title of host publicationCLEO
Subtitle of host publicationScience and Innovations, CLEO_SI 2013
StatePublished - Nov 18 2013
EventCLEO: Science and Innovations, CLEO_SI 2013 - San Jose, CA, United States
Duration: Jun 9 2013Jun 14 2013

Publication series

NameCLEO: Science and Innovations, CLEO_SI 2013

Other

OtherCLEO: Science and Innovations, CLEO_SI 2013
CountryUnited States
CitySan Jose, CA
Period6/9/136/14/13

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics

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  • Cite this

    Tian, Y., Fok, M. P., & Prucnal, P. R. (2013). A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding. In CLEO: Science and Innovations, CLEO_SI 2013 (CLEO: Science and Innovations, CLEO_SI 2013).