A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

Yue Tian; Mable P. Fok; Paul R. Prucnal

A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

Yue Tian, Mable P. Fok, Paul R. Prucnal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.

Original language	English (US)
Title of host publication	CLEO
Subtitle of host publication	Science and Innovations, CLEO_SI 2013
Pages	CTh4L.1
State	Published - 2013
Event	CLEO: Science and Innovations, CLEO_SI 2013 - San Jose, CA, United States Duration: Jun 9 2013 → Jun 14 2013

Publication series

Name	CLEO: Science and Innovations, CLEO_SI 2013

Other

Other	CLEO: Science and Innovations, CLEO_SI 2013
Country/Territory	United States
City	San Jose, CA
Period	6/9/13 → 6/14/13

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics

Cite this

@inproceedings{458fdf0366744bfdafc40271ce71069e,

title = "A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding",

abstract = "We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.",

author = "Yue Tian and Fok, {Mable P.} and Prucnal, {Paul R.}",

year = "2013",

language = "English (US)",

isbn = "9781557529725",

series = "CLEO: Science and Innovations, CLEO_SI 2013",

pages = "CTh4L.1",

booktitle = "CLEO",

note = "CLEO: Science and Innovations, CLEO_SI 2013 ; Conference date: 09-06-2013 Through 14-06-2013",

}

TY - GEN

T1 - A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

AU - Tian, Yue

AU - Fok, Mable P.

AU - Prucnal, Paul R.

PY - 2013

Y1 - 2013

N2 - We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.

AB - We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.

UR - http://www.scopus.com/inward/record.url?scp=84887497042&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84887497042&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84887497042

SN - 9781557529725

T3 - CLEO: Science and Innovations, CLEO_SI 2013

SP - CTh4L.1

BT - CLEO

T2 - CLEO: Science and Innovations, CLEO_SI 2013

Y2 - 9 June 2013 through 14 June 2013

ER -

A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

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