A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding

Yue Tian, Mable P. Fok, Paul R. Prucnal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We experimentally demonstrate a reconfigurable and timing-jitter insensitive AND/NOT gate based on tunable gain dynamics in a semiconductor optical amplifier and optical thresholding. The measured jitter tolerance is up to ±50 ps or ±25 ps for the AND/NOT gate.

Original languageEnglish (US)
Title of host publication2013 Conference on Lasers and Electro-Optics, CLEO 2013
PublisherIEEE Computer Society
ISBN (Print)9781557529725
DOIs
StatePublished - 2013
Event2013 Conference on Lasers and Electro-Optics, CLEO 2013 - San Jose, CA, United States
Duration: Jun 9 2013Jun 14 2013

Publication series

Name2013 Conference on Lasers and Electro-Optics, CLEO 2013

Other

Other2013 Conference on Lasers and Electro-Optics, CLEO 2013
CountryUnited States
CitySan Jose, CA
Period6/9/136/14/13

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials

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    Tian, Y., Fok, M. P., & Prucnal, P. R. (2013). A timing jitter insensitive logic gate using tunable gain dynamics in an SOA and optical thresholding. In 2013 Conference on Lasers and Electro-Optics, CLEO 2013 [6833442] (2013 Conference on Lasers and Electro-Optics, CLEO 2013). IEEE Computer Society. https://doi.org/10.1364/cleo_si.2013.cth4l.1