TY - GEN
T1 - A technology-aware and energy-oriented topology exploration for on-chip networks
AU - Wang, Hangsheng
AU - Peh, Li Shiuan
AU - Malik, Sharad
PY - 2005
Y1 - 2005
N2 - As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been identified to be a major design challenge. Network topologies have high impact on network power consumption. Technology scaling is another important factor that affects network power since each new technology changes semiconductor physical properties. As shown in this paper, these two aspects need to be considered synergistically. In this paper, we characterize the impact of process technologies on network energy for a range of topologies, starting from 2-dimensional meshes/tori, to variants of meshes/tori that incorporate higher dimensions, multiple hierarchies and express channels. We present a method which uses an analytical model to predict the most energy-efficient topology based on network size and architecture parameters for future technologies. Our model is validated against cycle-accurate network power simulation and shown to arrive at the same predictions. We also show how our method can be applied to actual parallel benchmarks with a case study. We see this work as a starting point for defining a roadmap of future on-chip networks. 1.
AB - As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been identified to be a major design challenge. Network topologies have high impact on network power consumption. Technology scaling is another important factor that affects network power since each new technology changes semiconductor physical properties. As shown in this paper, these two aspects need to be considered synergistically. In this paper, we characterize the impact of process technologies on network energy for a range of topologies, starting from 2-dimensional meshes/tori, to variants of meshes/tori that incorporate higher dimensions, multiple hierarchies and express channels. We present a method which uses an analytical model to predict the most energy-efficient topology based on network size and architecture parameters for future technologies. Our model is validated against cycle-accurate network power simulation and shown to arrive at the same predictions. We also show how our method can be applied to actual parallel benchmarks with a case study. We see this work as a starting point for defining a roadmap of future on-chip networks. 1.
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U2 - 10.1109/DATE.2005.40
DO - 10.1109/DATE.2005.40
M3 - Conference contribution
AN - SCOPUS:33645002018
SN - 0769522882
SN - 9780769522883
T3 - Proceedings -Design, Automation and Test in Europe, DATE '05
SP - 1238
EP - 1243
BT - Proceedings - Design, Automation and Test in Europe, DATE '05
T2 - Design, Automation and Test in Europe, DATE '05
Y2 - 7 March 2005 through 11 March 2005
ER -