A synthesis-based test generation and compaction algorithm for multifaults

Srinivas Devadas, Kurt Keutzer, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Several synthesis strategies are presented for the synthesis of flattenable and non-flattenable circuits for complete multifault testability, with associated compaction procedures. Experimental results are provided which indicate that a compacted multifault test set derived using these strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of these procedures, as compared to previous techniques.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages359-365
Number of pages7
ISBN (Print)0818691492, 9780818691492
DOIs
StatePublished - 1991
Externally publishedYes
EventProceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
Duration: Jun 17 1991Jun 21 1991

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Other

OtherProceedings of the 28th ACM/IEEE Design Automation Conference
CitySan Francisco, CA, USA
Period6/17/916/21/91

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Devadas, S., Keutzer, K., & Malik, S. (1991). A synthesis-based test generation and compaction algorithm for multifaults. In Proceedings - Design Automation Conference (pp. 359-365). (Proceedings - Design Automation Conference). Publ by IEEE. https://doi.org/10.1145/127601.127694