TY - JOUR
T1 - A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration
AU - Sorensen, Tyler
AU - Manocha, Aninda
AU - Tureci, Esin
AU - Orenes-Vera, Marcelo
AU - Aragon, Juan L.
AU - Martonosi, Margaret
N1 - Funding Information:
The authors thank the DECADES team, especially the SLD group led by Luca Carloni at Columbia and the Princeton Parallel Group led by David Wentzlaff at Princeton University. In particular, we thank Davide Giri for providing ESP accelerator performance models. We thank Opeoluwa Matthews, who was the lead designer and author of MosaicSim (and has since moved to an industry job at Apple). We thank Tae]un Ham as a past contributor to MosaicSim and as a consultant on some of our data supply features (e.g. DeSC). This work was supported in part by the DARPA SDH Program under agreement No. FA86S0-18-2-7862. This research was funded in part by the U.S. Government. Prof. Aragon has been partially supported by the Spanish State Research Agency under grant TIN2016-7S344R (AEl/FEDER, EU). The views and conclusions contained herein are those of the authors and should not be interpreted as representing the official policies or endorsements, either expressed or implied, of DARPA or the U.S. Government.
Publisher Copyright:
© 2020 Association on Computer Machinery.
PY - 2020/11/2
Y1 - 2020/11/2
N2 - As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly turning to heterogeneous parallelism and hardware-software co-design. These trends present new challenges for simulation-based performance assessments that are central to early-stage architectural exploration. Simulators must be lightweight to support heterogeneous combinations of general-purpose cores and specialized processing units. They must also support agile exploration of hardware-software co-design, i.e. changes in the programming model, compiler, ISA, and specialized hardware. To meet these challenges, we describe our compiler and simulator pair: DEC++ and MosaicSim. Together, they provide a lightweight, modular simulator for heterogeneous systems, offering accuracy and agility designed specifically for hardware-software co-design explorations. The simulator and corresponding compiler were developed as part of the DECADES project, a multi-team effort to design and tape out a new heterogeneous architecture. We will present two case-studies in important data-science applications where DEC++ and MosaicSim enable straightforward design space explorations for emerging full-stack systems.
AB - As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly turning to heterogeneous parallelism and hardware-software co-design. These trends present new challenges for simulation-based performance assessments that are central to early-stage architectural exploration. Simulators must be lightweight to support heterogeneous combinations of general-purpose cores and specialized processing units. They must also support agile exploration of hardware-software co-design, i.e. changes in the programming model, compiler, ISA, and specialized hardware. To meet these challenges, we describe our compiler and simulator pair: DEC++ and MosaicSim. Together, they provide a lightweight, modular simulator for heterogeneous systems, offering accuracy and agility designed specifically for hardware-software co-design explorations. The simulator and corresponding compiler were developed as part of the DECADES project, a multi-team effort to design and tape out a new heterogeneous architecture. We will present two case-studies in important data-science applications where DEC++ and MosaicSim enable straightforward design space explorations for emerging full-stack systems.
KW - hardware-software co-design. LLVM simulation
KW - heterogeneous systems
KW - performance modeling
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U2 - 10.1145/3400302.3415751
DO - 10.1145/3400302.3415751
M3 - Conference article
AN - SCOPUS:85097943775
SN - 1092-3152
VL - 2020-November
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
M1 - 9256600
T2 - 39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020
Y2 - 2 November 2020 through 5 November 2020
ER -