A router architecture for real-time communication in multicomputer networks

Keyphrases

• Real-time Communication 100%
• Packet Scheduler 66%
• Router Design 33%
• Verilog Simulation 33%
• End-to-end Delay Bound 33%
• Deadlock Avoidance Policy 33%
• Silicon Compilers 33%
• Table-driven 33%
• Scheduling Logic 33%
• Verilog Hardware Description Language 33%
• Multicast Routing 33%
• Buffer Requirements 33%

Computer Science

• End-to-End Delay 50%
• Multicast Routing 50%
• Deadlock Avoidance 50%