TY - GEN
T1 - A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz
AU - Sinangil, Mahmut E.
AU - Verma, Naveen
AU - Chandrakasan, Anantha P.
PY - 2008
Y1 - 2008
N2 - A 64kb SRAM array fabricated in 65nm low-power CMOS operates from 250mV to 1.2V. This wide supply range is enabled by a combination of circuits optimized for both sub-Vt and above-Vtregimes. Reconfigurable circuits are used extensively, as low voltage assist circuits are required for functionality, but they must not limit performance during high voltage operation. The SRAM operates at 20kHz with a 250m V supply and 200MHz with a 1.2V supply. Over this range the leakage power scales by more than 50X.
AB - A 64kb SRAM array fabricated in 65nm low-power CMOS operates from 250mV to 1.2V. This wide supply range is enabled by a combination of circuits optimized for both sub-Vt and above-Vtregimes. Reconfigurable circuits are used extensively, as low voltage assist circuits are required for functionality, but they must not limit performance during high voltage operation. The SRAM operates at 20kHz with a 250m V supply and 200MHz with a 1.2V supply. Over this range the leakage power scales by more than 50X.
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U2 - 10.1109/ESSCIRC.2008.4681847
DO - 10.1109/ESSCIRC.2008.4681847
M3 - Conference contribution
AN - SCOPUS:58049117797
SN - 9781424423620
T3 - ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
SP - 282
EP - 285
BT - ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
T2 - 34th European Solid-State Circuits Conference, ESSCIRC 2008
Y2 - 15 September 2008 through 19 September 2008
ER -