Abstract
A highly efficient pipelining processing approach for real-time image/video signal processing, called pipeline interleaving, is described. Image data from standard raster scan video input are distributed into local memory of processors in the way that the computation phase can be interleaved within the loading phase and pipelining can be fully exploited. Communication is minimized by using an overlap-save scheme. Two pipeline interleaving schemes for image/video processing are proposed. Scheme I can only use a small number of processing elements (PEs) to obtain moderate processing speed (102 approximately 103 MOPS). Scheme II can achieve an order of magnitude higher computation speed ( > 103 MOPS) by using more PEs. The structured mapping of several classes of algorithms for image/video processing onto the pipeline interleaved array architecture is discussed. The necessary real-time processing requirements for array size, memory, allocation, and computation complexity are derived. An implementation example of pipeline interleaving schemes on NEC video/image signal processors (40 MHz rate) is briefly discussed.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 3046-3049 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - 1990 |
| Event | 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: May 1 1990 → May 3 1990 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering