A Procedure for Placement of Standard-Cell VLSI Circuits

Alfred E. Dunlop; Brian W. Kernighan

doi:10.1109/TCAD.1985.1270101

A Procedure for Placement of Standard-Cell VLSI Circuits

Alfred E. Dunlop, Brian W. Kernighan

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273 Scopus citations

Abstract

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10–20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

Original language	English (US)
Pages (from-to)	92-98
Number of pages	7
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	4
Issue number	1
DOIs	https://doi.org/10.1109/TCAD.1985.1270101
State	Published - Jan 1985
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.1985.1270101

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@article{fe0046dcd10f4f46a54ba9cd84bebfb7,

title = "A Procedure for Placement of Standard-Cell VLSI Circuits",

abstract = "This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10–20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.",

author = "Dunlop, {Alfred E.} and Kernighan, {Brian W.}",

year = "1985",

month = jan,

doi = "10.1109/TCAD.1985.1270101",

language = "English (US)",

volume = "4",

pages = "92--98",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - A Procedure for Placement of Standard-Cell VLSI Circuits

AU - Dunlop, Alfred E.

AU - Kernighan, Brian W.

PY - 1985/1

Y1 - 1985/1

N2 - This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10–20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

AB - This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10–20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

UR - http://www.scopus.com/inward/record.url?scp=0021784846&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0021784846&partnerID=8YFLogxK

U2 - 10.1109/TCAD.1985.1270101

DO - 10.1109/TCAD.1985.1270101

M3 - Article

AN - SCOPUS:0021784846

SN - 0278-0070

VL - 4

SP - 92

EP - 98

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 1

ER -

A Procedure for Placement of Standard-Cell VLSI Circuits

Abstract

All Science Journal Classification (ASJC) codes

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