An architectural-level power model for interconnection network routers was developed. The model was applicable to a diverse range of router microarchitectures in on-chip, chip-to-chip and board-to-board networks. Experimental results showed that buffers were the largest power hog in routers and arbiter power was negligible under high network load. The model allowed researchers and designers to factor in power estimates when exploring different architectural tradeoffs.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering