A novel cache architecture with enhanced performance and security

Zhenghong Wang, Ruby Bei-Loh Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

143 Scopus citations

Abstract

Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent findings on efficient attacks based on information leakage in caches have also brought the security issue up front. Design for security introduces even more restrictions and typically leads to significant performance degradation. This paper presents a novel cache architecture that can simultaneously achieve the above goals. Specifically, cache miss rates are reduced with dynamic remapping and longer cache indices, access-time overhead overcome with astute low-level circuit design, and information leakage thwarted by a security-aware cache replacement algorithm together with the performance enhancing mechanisms. We present both theoretical analysis and experimental results, using the SPEC2000 suite to evaluate the cache miss behavior, and CACTI and HSPICE to validate the circuit design. Our results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache. At the same time it can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security. Additional benefits that the proposed cache architecture can bring, like fault tolerance and hot-spot mitigation, are also discussed briefly.

Original languageEnglish (US)
Title of host publication2008 Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41
Pages83-93
Number of pages11
Edition2008 PROCEEDINGS
DOIs
StatePublished - Dec 1 2008
Event2008 - 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41 - Lake Como, Italy
Duration: Nov 8 2008Nov 12 2008

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Number2008 PROCEEDINGS
ISSN (Print)1072-4451

Other

Other2008 - 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41
CountryItaly
CityLake Como
Period11/8/0811/12/08

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Cache
  • Computer architecture
  • Performance
  • Security
  • Side channel attacks

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    Wang, Z., & Lee, R. B-L. (2008). A novel cache architecture with enhanced performance and security. In 2008 Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41 (2008 PROCEEDINGS ed., pp. 83-93). [4771781] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; No. 2008 PROCEEDINGS). https://doi.org/10.1109/MICRO.2008.4771781