TY - JOUR
T1 - A New Transition Count Method for Testing of Logic Circuits
AU - Diamantaras, Konstantinos I.
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received July 27, 1989; revised January 29, 1990. This work was supported in part by the National Science Foundation under Grant MIP-8815674. This paper was recommended by Associate Editor F. Brglez. The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. IEEE Log Number 9040963.
PY - 1991/3
Y1 - 1991/3
N2 - In this paper we propose a new transition count method for detecting faults in single and multiple output logic circuits. It can be extended to sequential circuits in which scan design is incorporated. This method is called double transition count (DTC) testing for single output circuits, and multiple transition count (MTC) testing for multiple output circuits. We show that the detectability of faults obtained by DTC and MTC testing is the same as that obtained by conventional testing. Hence, this method does not result in any information loss although the set of output vectors is considerably compressed. Furthermore, the size of a DTC or MTC test is equal to the size of the equivalent conventional test since no test vectors need to be repeated. Finally, the basic test circuitry required is very simple, consisting of only one flip-flop, one OR gate, one inverter, and one switch per output.
AB - In this paper we propose a new transition count method for detecting faults in single and multiple output logic circuits. It can be extended to sequential circuits in which scan design is incorporated. This method is called double transition count (DTC) testing for single output circuits, and multiple transition count (MTC) testing for multiple output circuits. We show that the detectability of faults obtained by DTC and MTC testing is the same as that obtained by conventional testing. Hence, this method does not result in any information loss although the set of output vectors is considerably compressed. Furthermore, the size of a DTC or MTC test is equal to the size of the equivalent conventional test since no test vectors need to be repeated. Finally, the basic test circuitry required is very simple, consisting of only one flip-flop, one OR gate, one inverter, and one switch per output.
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U2 - 10.1109/43.67794
DO - 10.1109/43.67794
M3 - Article
AN - SCOPUS:0026130970
SN - 0278-0070
VL - 10
SP - 407
EP - 410
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 3
ER -