A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

We present a 65nm CMOS mixed-signal accelerator for first and hidden layers ofbinarized CNNs. Hidden layers support up to 512, 3 ×3 ×512 binary - input filters, and first layers support up to 64, 3×3 ×3 analog-input filters. Weight storage and multiplication with input activations is achieved within compact hardware, only 1.8 × larger than a 6T SRAM bit cell, and output activations are computed via capacitive charge sharing, requiring distribution of only a switch-control signal. Reduced data movement gives energy-efficiency of 658 (binary) / 0.95 TOPS/Wand throughput of 9438 (binary) / 10.64 GOPS for hidden / first layers.

Original languageEnglish (US)
Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages141-142
Number of pages2
ISBN (Electronic)9781538667002
DOIs
StatePublished - Oct 22 2018
Event32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
Duration: Jun 18 2018Jun 22 2018

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2018-June

Other

Other32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
CountryUnited States
CityHonolulu
Period6/18/186/22/18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2018). A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 141-142). [8502421] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502421