A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

Hossein Valavi; Peter J. Ramadge; Eric Nestler; Naveen Verma

doi:10.1109/VLSIC.2018.8502421

A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

119 Scopus citations

Abstract

We present a 65nm CMOS mixed-signal accelerator for first and hidden layers ofbinarized CNNs. Hidden layers support up to 512, 3 ×3 ×512 binary - input filters, and first layers support up to 64, 3×3 ×3 analog-input filters. Weight storage and multiplication with input activations is achieved within compact hardware, only 1.8 × larger than a 6T SRAM bit cell, and output activations are computed via capacitive charge sharing, requiring distribution of only a switch-control signal. Reduced data movement gives energy-efficiency of 658 (binary) / 0.95 TOPS/Wand throughput of 9438 (binary) / 10.64 GOPS for hidden / first layers.

Original language	English (US)
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	141-142
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502421
State	Published - Oct 22 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Other

Other	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	6/18/18 → 6/22/18

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2018.8502421

Cite this

Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2018). A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 141-142). Article 8502421 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502421

Valavi, Hossein ; Ramadge, Peter J. ; Nestler, Eric et al. / A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 141-142 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "We present a 65nm CMOS mixed-signal accelerator for first and hidden layers ofbinarized CNNs. Hidden layers support up to 512, 3 ×3 ×512 binary - input filters, and first layers support up to 64, 3×3 ×3 analog-input filters. Weight storage and multiplication with input activations is achieved within compact hardware, only 1.8 × larger than a 6T SRAM bit cell, and output activations are computed via capacitive charge sharing, requiring distribution of only a switch-control signal. Reduced data movement gives energy-efficiency of 658 (binary) / 0.95 TOPS/Wand throughput of 9438 (binary) / 10.64 GOPS for hidden / first layers.",

author = "Hossein Valavi and Ramadge, {Peter J.} and Eric Nestler and Naveen Verma",

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Valavi, H , Ramadge, PJ, Nestler, E & Verma, N 2018, A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502421, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 141-142, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIC.2018.8502421

A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. / Valavi, Hossein ; Ramadge, Peter J.; Nestler, Eric et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 141-142 8502421 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Valavi H , Ramadge PJ, Nestler E, Verma N. A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 141-142. 8502421. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2018.8502421

A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

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