TY - JOUR
T1 - A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system
AU - Verma, Naveen
AU - Shoeb, Ali
AU - Bohorquez, Jose
AU - Dawson, Joel
AU - Guttag, John
AU - Chandrakasan, Anantha P.
N1 - Funding Information:
Manuscript received August 24, 2009; revised January 15, 2010. Current version published March 24, 2010. This paper was approved by Guest Editor Ajith Amerasekera. The work of N. Verma was supported in part by the Intel Foundation Ph.D. Fellowship Program and NSERC. IC fabrication was provided by National Semiconductor Corporation.
PY - 2010/4
Y1 - 2010/4
N2 - This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 μ J per feature vector.
AB - This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 μ J per feature vector.
KW - 1/f noise
KW - Algorithm design and analysis
KW - Amplifiers
KW - Biomedical equipment
KW - Brain
KW - Choppers
KW - Digital signal processing
KW - Electroencephalography
KW - Low-noise amplifiers
KW - Low-power electronics
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U2 - 10.1109/JSSC.2010.2042245
DO - 10.1109/JSSC.2010.2042245
M3 - Article
AN - SCOPUS:77950193145
SN - 0018-9200
VL - 45
SP - 804
EP - 816
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 4
M1 - 5437484
ER -