A machine-learning classifier implemented in a standard 6T SRAM array

Jintao Zhang; Zhuo Wang; Naveen Verma

doi:10.1109/VLSIC.2016.7573556

A machine-learning classifier implemented in a standard 6T SRAM array

Jintao Zhang, Zhuo Wang, Naveen Verma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

133 Scopus citations

Abstract

This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.

Original language	English (US)
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509006342
DOIs	https://doi.org/10.1109/VLSIC.2016.7573556
State	Published - Sep 21 2016
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: Jun 14 2016 → Jun 17 2016

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2016-September

Other

Other	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	6/14/16 → 6/17/16

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/VLSIC.2016.7573556

Cite this

Zhang, J., Wang, Z., & Verma, N. (2016). A machine-learning classifier implemented in a standard 6T SRAM array. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 Article 7573556 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2016.7573556

@inproceedings{0755c6a70f2b463dbba0355ee6b2938c,

title = "A machine-learning classifier implemented in a standard 6T SRAM array",

abstract = "This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.",

author = "Jintao Zhang and Zhuo Wang and Naveen Verma",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

year = "2016",

month = sep,

day = "21",

doi = "10.1109/VLSIC.2016.7573556",

language = "English (US)",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016",

address = "United States",

}

Zhang, J, Wang, Z & Verma, N 2016, A machine-learning classifier implemented in a standard 6T SRAM array. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016., 7573556, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 6/14/16. https://doi.org/10.1109/VLSIC.2016.7573556

A machine-learning classifier implemented in a standard 6T SRAM array. / Zhang, Jintao; Wang, Zhuo; Verma, Naveen.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573556 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A machine-learning classifier implemented in a standard 6T SRAM array

AU - Zhang, Jintao

AU - Wang, Zhuo

AU - Verma, Naveen

PY - 2016/9/21

Y1 - 2016/9/21

N2 - This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.

AB - This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.

UR - http://www.scopus.com/inward/record.url?scp=84991000759&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84991000759&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2016.7573556

DO - 10.1109/VLSIC.2016.7573556

M3 - Conference contribution

AN - SCOPUS:84991000759

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

Y2 - 14 June 2016 through 17 June 2016

ER -

A machine-learning classifier implemented in a standard 6T SRAM array

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this