A machine-learning classifier implemented in a standard 6T SRAM array

Jintao Zhang, Zhuo Wang, Naveen Verma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

56 Scopus citations

Abstract

This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.

Original languageEnglish (US)
Title of host publication2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006342
DOIs
StatePublished - Sep 21 2016
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: Jun 14 2016Jun 17 2016

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2016-September

Other

Other30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
CountryUnited States
CityHonolulu
Period6/14/166/17/16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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