TY - JOUR

T1 - A Linear Systolic Array for Real-Time Morphological Image Processing

AU - Diamantaras, K. I.

AU - Kung, S. Y.

N1 - Funding Information:
⁄This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.

PY - 1997

Y1 - 1997

N2 - Mathematical morphology has proven to be a very useful tool for applications such as smoothing, image skeletonization, pattern recognition, machine vision, etc. In this paper we present a 1-dimensional systolic architecture for the basic gray-scale morphology operations: dilation and erosion. Most other morphological operations like opening and closing, are also supported by the architecture since these operations are combinations of the basic ones. The advantages of our design stem from the fact that it has pipeline period α = 1 (i.e., 100% processor utilization), it requires simple communications, and it is exploiting the simplicity of the morphological operations to make it possible to implement them in a linear target machine although the starting algorithm is a generalized 2-D convolution. We also propose a Locally Parallel Globally Sequential (LPGS) partitioning strategy for the best mapping of the algorithm onto the architecture. We conclude that for this particular problem LPGS is better than LSGP in a practical sense (pinout, memory requirement, etc.). Furthermore, we propose a chip design for the basic component of the array that will allow real-time video processing for 8- and 16-bit gray-level frames of size 512 × 512, using only 32 processors in parallel. The design is easily scalable so it can be custom-taylored to fit the requirement of each particular application.

AB - Mathematical morphology has proven to be a very useful tool for applications such as smoothing, image skeletonization, pattern recognition, machine vision, etc. In this paper we present a 1-dimensional systolic architecture for the basic gray-scale morphology operations: dilation and erosion. Most other morphological operations like opening and closing, are also supported by the architecture since these operations are combinations of the basic ones. The advantages of our design stem from the fact that it has pipeline period α = 1 (i.e., 100% processor utilization), it requires simple communications, and it is exploiting the simplicity of the morphological operations to make it possible to implement them in a linear target machine although the starting algorithm is a generalized 2-D convolution. We also propose a Locally Parallel Globally Sequential (LPGS) partitioning strategy for the best mapping of the algorithm onto the architecture. We conclude that for this particular problem LPGS is better than LSGP in a practical sense (pinout, memory requirement, etc.). Furthermore, we propose a chip design for the basic component of the array that will allow real-time video processing for 8- and 16-bit gray-level frames of size 512 × 512, using only 32 processors in parallel. The design is easily scalable so it can be custom-taylored to fit the requirement of each particular application.

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M3 - Article

AN - SCOPUS:0031222122

SN - 1387-5485

VL - 17

SP - 43

EP - 55

JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

IS - 1

ER -