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Nanoscale CMOS
100%
Hybrid Nano
100%
Random Access Memory
100%
Dynamically Reconfigurable Systems
100%
Nanotechnology
50%
Runtime Reconfiguration
50%
Reconfigurable Architectures
50%
On chip
33%
Logic Folding
33%
Logic Density
33%
Temporal Logic
33%
Fabrication Methods
33%
Latency
16%
Rapid Progress
16%
Order of Magnitude
16%
High Performance
16%
Circuit Design
16%
Nanofabrication Techniques
16%
Carbon Nanotubes
16%
Non-volatile
16%
Nanodevices
16%
CMOS Logic
16%
Photolithography
16%
Design Flow
16%
Power Consumption
16%
Reconfiguration
16%
Resource Utilization
16%
Performance Demands
16%
Hybrid Design
16%
Nanocircuits
16%
Good Compatibility
16%
Defect Levels
16%
Memory Phases
16%
Magnetic Random Access Memory
16%
Resource Performance
16%
Automatic Design
16%
Phase Change Random Access Memory (PCRAM)
16%
Fast Reading
16%
Hybrid chip
16%
Results-based
16%
Promising Directions
16%
On-chip Storage
16%
Computer Science
Random Access Memory
100%
Reconfigurable System
100%
Reconfiguration
57%
reconfigurable architecture
42%
Temporal Logic
28%
Experimental Result
14%
Storage Configuration
14%
Nonvolatile
14%
Power Consumption
14%
Resource Utilisation
14%
Automatic Design
14%
Material Science
Electronic Circuit
100%
Density
66%
Carbon Nanotube
33%
Nanodevice
33%
Phase-Change Memory
33%