Rapid progress is being made in the area of nanoelectronic circuit design. However, nanofabrication techniques are not mature yet. Thus, large-scale fabrication of such circuits is not feasible. To ease fabrication and overcome the expected high defect levels in nanotechnology, hybrid nono/CMOS reconfigurable architecture are attractive, especially if they can be fabricated using photolithography. This chapter describes one such architecture called NATURE. Unlike traditional reconfigurable architectures that can only support partial or coarse-grain dynamic reconfiguration, NATURE can support cycle-level dynamic reconfiguration. This allows the amount of functionality mapped in the same chip area to increase by more than an order of magnitude. The chapter also discusses how arbitrary logic circuits can be efficiently mapped to NATURE.
All Science Journal Classification (ASJC) codes
- Dynamic reconfiguration
- Logic folding
- Nano RAM