Abstract
High-density SRAMs utilize aggressively small bit-cells, which are subject to extreme variability, degrading their read SNM and read-current. Additionally, array performance is also limited by sense-amplifier offset and strobe-timing uncertainty. This paper, presents a sense-amplifier that targets all of these performance degradations: specifically, simple offset compensation reduces sensitivity to variation while imposing minimal loading on high-speed nodes; stable internal voltage references serve as an internal means to self-trigger regeneration to avoid tracking mismatch in an external strobe-path; precise small-signal detection withstands small read-currents so that other bit-cell parameters can be optimized; and single-ended sensing provides compatibility to asymmetric bit-cells, which can have improved operating margins. The design is integrated with a 64-kb high-density array composed of 0.25 $μ{m}}{2} $ 6T bit-cells. A prototype, in low-power 45 nm CMOS, compares its performance with a conventional sense-amplifier, demonstrating an improvement of 4X in access-time sigma and 34% in overall worst case access time.
Original language | English (US) |
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Article number | 4735563 |
Pages (from-to) | 163-173 |
Number of pages | 11 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 44 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2009 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Keywords
- Auto-zeroing
- Device variation
- Offset compensation
- SRAM
- Sense-amplifier