TY - GEN
T1 - A frequency-reconfigurable mm-Wave power amplifier with active-impedance synthesis in an asymmetrical non-isolated combiner
AU - Chappidi, Chandrakanth Reddy
AU - Sengupta, Kaushik
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/2/23
Y1 - 2016/2/23
N2 - A frequency-agile mm-Wave power amplifier capable of reconfiguring itself to operate near-optimally over a wide range of tunable frequencies, yet producing output power >22dBm with PAE>20%, is useful for a wide range of applications in reconfigurable communication systems supporting multi-Gb/s over large links to hyper-spectral sensing and imaging. While recent works have demonstrated high efficiency in Watt-level mm-Wave power amplifiers [1-5], most of the architectures operate over a limited frequency range, primarily dominated by the bandwidth of the output-matching or combiner networks. A frequency-agile power amplifier, therefore, needs a widely reconfigurable, yet an efficient output network, which is difficult to achieve with on-chip variable passives due to their poor quality factors in silicon IC processes. In this paper, we present an architecture where an optimal impedance at the output of each unit cell is synthesized exploiting their interaction in a non-isolated power-combiner network. By controlling the amplitude and phase of unit cells, close-to-optimal impedances can be synthesized over a wide operating range at mm-Wave frequencies thus enabling frequency agility. The chip is implemented in a 0.13μm SiGe BiCMOS process and achieves Psat>22dBm between 40 and 65GHz and peak PAE>25% between 40 and 60GHz.
AB - A frequency-agile mm-Wave power amplifier capable of reconfiguring itself to operate near-optimally over a wide range of tunable frequencies, yet producing output power >22dBm with PAE>20%, is useful for a wide range of applications in reconfigurable communication systems supporting multi-Gb/s over large links to hyper-spectral sensing and imaging. While recent works have demonstrated high efficiency in Watt-level mm-Wave power amplifiers [1-5], most of the architectures operate over a limited frequency range, primarily dominated by the bandwidth of the output-matching or combiner networks. A frequency-agile power amplifier, therefore, needs a widely reconfigurable, yet an efficient output network, which is difficult to achieve with on-chip variable passives due to their poor quality factors in silicon IC processes. In this paper, we present an architecture where an optimal impedance at the output of each unit cell is synthesized exploiting their interaction in a non-isolated power-combiner network. By controlling the amplitude and phase of unit cells, close-to-optimal impedances can be synthesized over a wide operating range at mm-Wave frequencies thus enabling frequency agility. The chip is implemented in a 0.13μm SiGe BiCMOS process and achieves Psat>22dBm between 40 and 65GHz and peak PAE>25% between 40 and 60GHz.
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U2 - 10.1109/ISSCC.2016.7418048
DO - 10.1109/ISSCC.2016.7418048
M3 - Conference contribution
AN - SCOPUS:84962786566
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 344
EP - 345
BT - 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
Y2 - 31 January 2016 through 4 February 2016
ER -