A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps

Engineering

• Fine Grain 100%
• Field Programmable Gate Arrays 100%
• Application Specific Integrated Circuit 100%
• Interconnects 40%
• Dynamic Reconfiguration 40%
• Reconfigurability 20%
• Array Architecture 20%
• Electric Power Utilization 20%
• Bridging 20%
• Lookup Table 20%
• Reliability Availability and Maintainability (Reliability Engineering) 20%

Computer Science

• reconfigurable architecture 100%
• Application Specific Integrated Circuit 100%
• Field Programmable Gate Arrays 100%
• Dynamic Reconfiguration 40%
• Logic Element 40%
• Hardware Resource 20%
• Temporal Logic 20%
• Table Lookup 20%
• Full Advantage 20%
• Reconfigurable Logic 20%
• Dynamic Power Consumption 20%

Keyphrases

• Static RAM 20%
• Hybrid CMOS 20%
• Large Delay 20%
• Area Usage 20%