A fast and low-cost testing technique for core-based system-chips

Indradeep Ghosh, Sujit Dey, Niraj K. Jha

Research output: Contribution to journalArticlepeer-review

29 Scopus citations


Abstract-This paper proposes a new methodology for testing a core-based system-chip, targeting the simultaneous reduction of test area overhead and test application time. At the core level, testability and transparency can be achieved by the core provider by reusing existing logic inside the core, providing different versions of the core having different area overheads and transparency latencies. The technique analyzes the topology of the system-chip to select the core versions that best meet the user's desired test area overhead and test application time objectives. Application of the method to example system-chips demonstrates the ability to design highly testable system-chips with minimized test area overhead, minimized test application time, or a desired tradeoff between the two. Significant reduction in area overhead and test application time compared to existing system-chip testing techniques is also demonstrated. Index Terms-.

Original languageEnglish (US)
Pages (from-to)863-877
Number of pages15
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number8
StatePublished - 2000
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


  • Cores
  • Design for testability
  • Intellectual property
  • System-chip
  • Testing, transparency


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