A dynamic compilation framework for controlling microprocessor energy and performance

Qiang Wu, V. J. Reddi, Youfeng Wu, Jin Lee, Dan Connors, David Brooks, Margaret Rose Martonosi, Douglas W. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

121 Scopus citations

Abstract

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrialstrength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3X-5X better than static voltage scaling, and is more than 2X (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control.

Original languageEnglish (US)
Title of host publicationMICRO-38
Subtitle of host publicationProceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture
Pages271-282
Number of pages12
DOIs
StatePublished - Dec 1 2005
EventMICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture - Barcelona, Spain
Duration: Nov 12 2005Nov 16 2005

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

OtherMICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture
CountrySpain
CityBarcelona
Period11/12/0511/16/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Wu, Q., Reddi, V. J., Wu, Y., Lee, J., Connors, D., Brooks, D., Martonosi, M. R., & Clark, D. W. (2005). A dynamic compilation framework for controlling microprocessor energy and performance. In MICRO-38: Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 271-282). [1540966] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2005.7