TY - GEN
T1 - A case for runtime validation of hardware
AU - Malik, Sharad
PY - 2006
Y1 - 2006
N2 - Increasing hardware design complexity has resulted in significant challenges for hardware design verification. The growing "verification gap" between the complexity of what we can verify and what we can fabricate/design is indicative of a crisis that is likely to get only worse with increasing complexity. A variety of methodology and tool solutions have been proposed to deal with this crisis, but there is little optimism that a single solution or even a set of cooperative solutions will be scalable to enable future design verification to be cost effective. It is time we reconcile ourselves to the fact that hardware, like software, will be shipped with bugs in it. One possible solution to deal with this inevitable scenario is to provide support for runtime validation that detects functional failures at runtime and then recovers from such failures, Such runtime validation hardware will increasingly be used to handle dynamic operational failures caused by reduced reliability of devices due to large process variations as well as increasing soft errors. Expanding the use of such hardware to deal with functional design failures provides for an on-chip insurance policy when design errors inevitably slip through the verification process. This paper will discuss the strengths and weaknesses of this form of design validation, some possible forms this may take, and implications on design methodology.
AB - Increasing hardware design complexity has resulted in significant challenges for hardware design verification. The growing "verification gap" between the complexity of what we can verify and what we can fabricate/design is indicative of a crisis that is likely to get only worse with increasing complexity. A variety of methodology and tool solutions have been proposed to deal with this crisis, but there is little optimism that a single solution or even a set of cooperative solutions will be scalable to enable future design verification to be cost effective. It is time we reconcile ourselves to the fact that hardware, like software, will be shipped with bugs in it. One possible solution to deal with this inevitable scenario is to provide support for runtime validation that detects functional failures at runtime and then recovers from such failures, Such runtime validation hardware will increasingly be used to handle dynamic operational failures caused by reduced reliability of devices due to large process variations as well as increasing soft errors. Expanding the use of such hardware to deal with functional design failures provides for an on-chip insurance policy when design errors inevitably slip through the verification process. This paper will discuss the strengths and weaknesses of this form of design validation, some possible forms this may take, and implications on design methodology.
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U2 - 10.1007/11678779_3
DO - 10.1007/11678779_3
M3 - Conference contribution
AN - SCOPUS:33745517171
SN - 3540326049
SN - 9783540326045
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 30
EP - 42
BT - Hardware and Software, Verification and Testing - First International Haifa Verification Conference, Revised Selected Papers
T2 - 1st International Haifa Verification Conference on Hardware and Software, Verification and Testing
Y2 - 13 November 2005 through 16 November 2005
ER -