TY - GEN
T1 - A 65nm Sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter
AU - Kwong, Joyce
AU - Ramadass, Yogesh
AU - Verma, Naveen
AU - Koesler, Markus
AU - Huber, Korbinian
AU - Moormann, Hans
AU - Chandrakasan, Anantha
PY - 2008
Y1 - 2008
N2 - A 65nm sub-Vt SoC integrates an on-chip, switched capacitor DC-DC converter with a 16b microcontroller and 128kb SRAM. The core logic is verified with a custom sub-Vt timing methodology. Functional down to 0.3V, the chip achieves 1 μW standby power at minimum Vdd. The converter realizes 75% efficiency at the minimum energy voltage of 0.5V
AB - A 65nm sub-Vt SoC integrates an on-chip, switched capacitor DC-DC converter with a 16b microcontroller and 128kb SRAM. The core logic is verified with a custom sub-Vt timing methodology. Functional down to 0.3V, the chip achieves 1 μW standby power at minimum Vdd. The converter realizes 75% efficiency at the minimum energy voltage of 0.5V
UR - http://www.scopus.com/inward/record.url?scp=49549093629&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=49549093629&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2008.4523185
DO - 10.1109/ISSCC.2008.4523185
M3 - Conference contribution
AN - SCOPUS:49549093629
SN - 9781424420100
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 318
EP - 320
BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2008 IEEE International Solid State Circuits Conference, ISSCC
Y2 - 3 February 2008 through 7 February 2008
ER -