A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy

Naveen Verma; Anantha P. Chandrakasan

doi:10.1109/ISSCC.2007.373427

A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy

Naveen Verma, Anantha P. Chandrakasan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

163 Scopus citations

Abstract

A 65nm 256kb 8T SRAM operates in sub-V_t at 350mV. Peripheral assists eliminate sub-V_t bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.

Original language	English (US)
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	328-330
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373427
State	Published - 2007
Externally published	Yes
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: Feb 11 2007 → Feb 15 2007

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	2/11/07 → 2/15/07

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373427

Cite this

Verma, N., & Chandrakasan, A. P. (2007). A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 328-330). Article 4242398 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373427

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abstract = "A 65nm 256kb 8T SRAM operates in sub-Vt at 350mV. Peripheral assists eliminate sub-Vt bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.",

author = "Naveen Verma and Chandrakasan, \{Anantha P.\}",

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series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "328--330",

booktitle = "2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",

address = "United States",

note = "54th IEEE International Solid-State Circuits Conference, ISSCC 2007 ; Conference date: 11-02-2007 Through 15-02-2007",

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Verma, N & Chandrakasan, AP 2007, A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242398, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 328-330, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 2/11/07. https://doi.org/10.1109/ISSCC.2007.373427

A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy. / Verma, Naveen; Chandrakasan, Anantha P.
2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 328-330 4242398 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Verma N, Chandrakasan AP. A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 328-330. 4242398. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373427

A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy

Abstract

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All Science Journal Classification (ASJC) codes

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