A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy

Naveen Verma, Anantha P. Chandrakasan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

140 Scopus citations

Abstract

A 65nm 256kb 8T SRAM operates in sub-Vt at 350mV. Peripheral assists eliminate sub-Vt bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.

Original languageEnglish (US)
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages328-330
Number of pages3
ISBN (Print)1424408539, 9781424408535
DOIs
StatePublished - 2007
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: Feb 11 2007Feb 15 2007

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period2/11/072/15/07

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Verma, N., & Chandrakasan, A. P. (2007). A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 328-330). [4242398] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373427