TY - GEN
T1 - A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy
AU - Verma, Naveen
AU - Chandrakasan, Anantha P.
PY - 2007
Y1 - 2007
N2 - A 65nm 256kb 8T SRAM operates in sub-Vt at 350mV. Peripheral assists eliminate sub-Vt bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.
AB - A 65nm 256kb 8T SRAM operates in sub-Vt at 350mV. Peripheral assists eliminate sub-Vt bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.
UR - http://www.scopus.com/inward/record.url?scp=34548858947&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548858947&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2007.373427
DO - 10.1109/ISSCC.2007.373427
M3 - Conference contribution
AN - SCOPUS:34548858947
SN - 1424408539
SN - 9781424408535
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 328
EP - 330
BT - 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Y2 - 11 February 2007 through 15 February 2007
ER -